This invention relates in general to electrically erasable and programmable read-only memories ("EEPROMs") and in particular, to a method and circuit which minimizes the programming time for individual and blocks of memory cells in an EEPROM by simultaneously programming and verifying the programming of each EEPROM cell being programmed.
The relative advantages of EEPROM technology over other solid-state memory technologies, are well known. For example, unlike dynamic random access memories ("DRAMs") and static random access memories ("SRAMs"), EEPROMs are non-volatile memory devices. Therefore, unlike DRAMs and SRAMs, information stored in an EEPROM is not lost when power to the EEPROM is turned off.
Also, unlike masked read-only memories ("ROMs") and programmable read-only memories ("PROMs"), neither of which are erasable, and electrically programmable read-only memories ("EPROMs"), which require special fixtures and ultra-violet light for erasing, EEPROMs are both electrically programmable and electrically erasable. Therefore, unlike ROMs, PROMs and EPROMs, an EEPROM can be readily erased and reprogrammed incircuit, i.e., without removing the EEPROM from a printed circuit board ("PCB").
The number of times that a conventional EEPROM cell can be erased and reprogrammed, however, is limited (e.g., 10,000 to 100,000). Presumably, such limitation is attributable to charge accumulated in a first isolation layer between a floating gate and a drain region of the EEPROM cell, built up by repeated programming of the EEPROM cell, and/or to charge accumulated in a second isolation layer between the floating gate and an erase gate of the EEPROM cell, built up by repeated erasing of the EEPROM cell.
In addition to limiting the useful life of an EEPROM cell, charge accumulation in the isolation layers also increases the time required to effectively program and erase the EEPROM cell. Consequently, since there may be significant variation in the number of times that different cells in the EEPROM cell array are programmed and/or erased, there may be, as a result, significant variation in the time required to effectively program and/or erase different cells in the EEPROM cell array.
This variation in the required programming and erasing times between different cells in the EEPROM cell array over the operational life of the EEPROM causes significant control problems for circuitry designed to program or erase selected cells in the EEPROM cell array. For example, if the programming circuitry is designed such that it provides a programming pulse of the same magnitude and width each time a cell in the EEPROM cell array is to be programmed, then the pulse would have to be of a sufficient magnitude and width to ensure that even the hardest to program EEPROM cells get programmed. Typically, such a pulse width or duration may need to be as long as 100 .mu.sec.
Since most cells, especially virgin cells (i.e., EEPROM cells which have never been programmed), could be effectively programmed much sooner than 100 .mu.sec., such an extended programming period not only unduly delays the programming process, but also reduces the reliability and life of the cells. Accordingly, iterative program-verify techniques using a series of shorter pulses (e.g., 2 .mu.sec.) have been developed wherein between each of the shorter pulses a read verification of the cell is conducted. Upon such read verification, if the cell has not programmed, then the cell is subjected to another short pulse. On the other hand, if the cell has programmed, then the pulses stop.
Although the above discussion has been limited, for simplicity, to bi-state EEPROM cells, it is also applicable to the programming of multi-state EEPROM cells. A description of multi-state EEPROM cells and an example of an iterative program-verify technique for programming such cells is described in U.S. Pat. No. 5,043,940, entitled "Flash EEPROM Memory Systems Having Multistate Storage Cells," issued to Harari and assigned to the same assignee as the present invention, which patent is herein incorporated by reference.
Iterative program-verify techniques, however, provide less than optimal programming operation. The shifting back and forth between programming and reading modes typically requires processor intervention, thus interrupting the processor from other important tasks, and the accumulated time spent in the reading modes unduly adds to the overall programming time for the EEPROM cell. Consequently, although such iterative program-verify techniques are improvements over the single pulse of fixed magnitude and duration approach, they are still clearly worthy of further improvement.